An eight-layer PCB has eight copper layers. The solder mask, legend, dielectric sheets, and mechanical drawing layers do not add to that count. Eight layers offer more room to allocate signals and reference conductors, but the number alone says little about electrical performance. A poorly planned eight-layer board can still contain interrupted return paths and impractical layer transitions.
Start with a routing budget
List interfaces, power domains, connectors, dense packages, and mechanical restrictions before assigning layer names. Identify which signals need controlled impedance and which connections must remain especially short. Estimate the routing channels required to escape the largest package. This produces a reason for each signal layer instead of relying on a familiar stack drawing.
Next, identify the reference for every important routing layer. A power plane is not automatically an adequate substitute for a continuous ground reference in every application. Review how the signal and its return current will cross connector regions, plane openings, and changes of layer. Resolve those transitions before dense routing obscures them.
Turn the arrangement into a manufacturing stack
| Design question | Information needed from fabrication |
|---|---|
| Can the target geometry be routed? | Finished dielectric spacing and copper thickness |
| Can the board fit the enclosure? | Total finished thickness and tolerance |
| Can the package escape use the proposed vias? | Permitted hole spans, pads, and filling process |
| Can impedance be verified? | Coupon arrangement, test method, and reporting scope |
Eight layers do not automatically require HDI. Conversely, an eight-layer HDI construction needs more information than a through-hole multilayer. Würth Elektronik publishes distinct eight-layer microvia constructions; this illustrates why the layer count cannot identify the via architecture by itself.
Make the prototype answer a production question
Use a prototype stack that represents the intended production build. Changing dielectric thickness, foil, via structure, or surface finish after testing may invalidate the conclusions that mattered. If a substitute is unavoidable, write down which measurements remain representative and which require repetition.
- Approve the fabrication stack and impedance geometry before final routing.
- Check each critical net’s reference and every layer transition.
- Export copper, drill spans, outline, and stack notes from the same revision.
- Review returned manufacturing questions against the layout, not only the drawing.
- Retain coupon results and board identification with the prototype measurements.
A passing bare-board electrical test establishes connectivity within its test coverage. It does not establish interface margin, power integrity, or enclosure compatibility. Include those checks in the prototype plan and link the results to the approved stack. Our stackup planning guide explains the information to release together.
Move from reading to a build-ready project
Use the fabrication and assembly checklists to prepare drawings, production files and test requirements.
Open the DFM checklist