Assigning the RMII Reference Clock Source and Direction

An Ethernet PHY can establish a cable link while communication with the processor still fails because the RMII reference clock is missing, incorrectly directed, or configured for the wrong source arrangement. Treat the MAC to PHY clock path as a separate interface from the cable side link.

Draw one clock owner

Identify the device that generates the reference clock and every device that receives it. Record the required frequency, pin direction, electrical levels, and enable state. Do not infer direction from a net name such as REFCLK; the same function can be an input or output in different configurations.

The TI DP83825I data sheet describes RMII clock arrangements including a mode with a 50 MHz output clock and modes using an external reference. Use the selected PHY and processor documentation together when choosing a supported topology.

Check startup configuration

Verify the strap or register state that establishes the PHY clock mode. Review processor pin multiplexing and whether its clock output is active before the PHY needs it. A design can create a circular dependency if the processor waits for the PHY while the PHY waits for a processor generated clock.

Include reset behavior. Determine whether reset changes clock output availability or pin direction, and whether the receiving device tolerates that interval. Avoid connecting two active clock outputs because their nominal frequency happens to match.

Measure at both receiving interfaces

Observe the reference clock at the relevant pins with a suitable probe. Check frequency, duty cycle, voltage levels, and startup timing against the actual specifications. A waveform observed only at the oscillator does not establish its quality after routing and loading.

Capture transmit or receive data relative to the clock used by its receiver. Review setup and hold with the correct timing reference, including board delay and device output delay. Do not assume that every connection should be length matched to the same target without understanding that relationship.

Separate cable and RMII evidence

Read PHY status to establish cable link state, then verify processor transmit and receive behavior independently. Use controlled packet traffic and inspect error counters where available. A link LED confirms only part of the system.

Save the clock topology, mode settings, reset sequence, timing captures, and traffic results. A useful bring up record identifies which component owns the clock in every state and demonstrates that each receiver sees a valid reference. That removes an entire class of apparent Ethernet failures before more complicated protocol debugging begins.