Assigning RGMII Clock Delay to the MAC, PHY, or PCB

An RGMII interface can have carefully matched traces and still fail because the required clock to data relationship is missing or inserted twice. The timing depends on the combined MAC, PHY, and board configuration. Establish responsibility for the delay in each direction before adjusting register values experimentally.

Separate transmit and receive paths

Draw each source, its data and clock outputs, the interconnect, and the receiving pins. Use physical signal direction alongside TX and RX labels because device documentation may describe those labels from different perspectives.

The TI DP83867 troubleshooting guide pairs MAC and PHY align and shift modes to establish the intended timing relationship. The selected configuration must account for both devices rather than enabling internal delay simply because the feature is available.

Build a complete timing budget

List source clock to data timing, any intentional internal delay, relative PCB propagation, receiver setup and hold requirements, and uncertainty. Keep package and board contributions consistent with the reference planes used by the data sheets.

If a board intentionally delays the clock trace and firmware also enables an internal shift, both contributions affect the receiver. Conversely, removing a trace delay during layout cleanup requires checking whether another element now supplies the intended offset.

Read the active configuration

Record strap selections, boot firmware writes, operating system driver settings, and final register values. A device tree property or startup default can change the delay after an earlier diagnostic read. Capture the values after normal initialization finishes.

Check each direction independently. Successful traffic in one direction does not prove the other clock and data relationship. Also confirm the MAC interface voltage and configured link mode while reviewing timing.

Measure and verify at the receiver

Observe clock and representative data at an appropriate receiving reference point with probes suitable for the edge rate. Inspect both clock edges because RGMII transfers data on both. Avoid inferring timing directly from trace length without the relevant propagation model.

Exercise the supported link speeds and representative traffic while watching error counters. Include operating conditions that affect delay margin. Save the timing budget, board delay assumptions, active configuration, and measured relationship.

A successful result identifies where the required delay is created and demonstrates acceptable setup and hold margin at the receiving device. It should remain understandable after a PHY replacement or firmware update. A link that becomes reliable only after an undocumented delay sweep has not yet established which configuration the board actually requires.