Matching PCIe Reference Clock Architecture and Spread Spectrum Settings

Two PCIe devices can each receive a nominally correct reference clock and still use an incompatible clocking arrangement. The relationship between the clocks matters alongside their individual quality. Establish the architecture and supported link modes before selecting spread spectrum settings or interpreting a reference-clock measurement.

Classify the clock relationship

The Renesas application note on PCIe clocking architectures distinguishes common clock from separate reference clocks. Separate reference no spread operation is SRNS; separate reference independent spread operation is SRIS. These architectures impose different requirements on the participating components.

Draw the source and distribution path for the root complex and endpoint. Include clock generators, buffers, connectors, and any PLL that changes the relationship. A shared oscillator somewhere upstream does not by itself describe the final clocks delivered to the two devices.

Check support at both ends

Read the endpoint and root-complex documentation for the intended PCIe generation and architecture. Record required configuration fields and firmware assumptions. A component’s support for one architecture at one operating mode should not be extended to every mode without evidence.

Check switches, retimers, and cable assemblies in the path as well. The architecture must be valid for the complete connection rather than only the two most visible components.

Apply spread settings consistently

Record whether spreading is enabled, its supported profile, and which clocks share the same modulation. Avoid treating an average frequency measurement as proof that the spreading relationship is correct.

For example, replacing one clock source with an independent oscillator can change the architecture even when both labels still read the same nominal frequency. That change requires a support and configuration review, not merely a new frequency measurement.

Measure using the relevant method

Use the jitter and clock requirements applicable to the selected architecture, generation, and component. Preserve instrument filtering and analysis settings. A generic integrated jitter value without its method cannot establish PCIe suitability.

Capture startup and clock-enable behavior in addition to steady operation. Confirm the relationship during supported power management and restart sequences, when a clock may be stopped or reconfigured.

Finally, exercise link training and sustained traffic across the supported arrangements. Record negotiated speed, width, retraining, and error status. A link that falls back to a slower mode can hide a configuration or margin problem.

Save the clock tree, architecture declaration, device support references, spread settings, and measured results. The release record should make the relationship between the two reference clocks explicit so later component substitutions cannot silently change the operating architecture.