A digital isolator can reproduce logic correctly after both sides are powered while producing an unwanted control level during startup. The receiving circuit may already be active when the transmitting side is off. Review those states explicitly, especially for reset, enable, chip-select and direction-control signals.

Use the complete ordering code

Identify the exact isolator variant and its documented default output behavior. The Texas Instruments ISO7741 family provides a concrete example: variants with and without an F suffix have different default output levels when input power or signal is lost, subject to the functional conditions in the datasheet. That naming convention should not be assumed for other families.

Check output-enable behavior separately from the default transmitted state. A disabled output may be high impedance rather than driven to the default level. The receiving circuit’s pullup or pulldown then becomes part of the state definition.

Build a power-state table

List input side off and output side on, the reverse combination, both on, both off and transitions between them. Include supply ramps, brownout and reset if they are part of the required operating envelope. For each state, record the receiving pin’s expected level and the evidence supporting it.

Do not infer a defined logic level below a device’s specified operating conditions unless the documentation guarantees it. If the system requires a particular state throughout a transition, provide a circuit and verification method that establishes it.

Follow the state into the receiver

An idle high signal can be appropriate for an active-low chip select and inappropriate for an active-high enable. Review polarity at the final receiving function, including any inverter or transceiver between the isolator and load. A schematic net name is not sufficient evidence of the resulting behavior.

Check pull resistors, input leakage and enable timing. If the receiving device also starts unpredictably, changing the isolator’s default variant may address only one contributor. Consider which circuit is responsible for holding the system in its intended startup state.

Observe transitions on representative hardware

Capture both supplies, relevant enables and the receiving signal while applying the approved startup and shutdown sequences. Test loss of input-side power while the output side remains active. Record brief pulses as well as final steady levels, using a time scale that can reveal them.

Keep the ordering code, state table and measured transitions with the interface review. A substitution that preserves channel count and isolation rating may still change default logic behavior. Acceptance should cover what the receiving circuit does during the supported power states, not only the quality of a steady data stream.

Move from reading to a build-ready project

Use the fabrication and assembly checklists to prepare drawings, production files and test requirements.

Open the DFM checklist