Investigating Miller Induced Turn On in an Off MOSFET

An off MOSFET can experience a gate voltage excursion when its drain voltage changes quickly. Current coupled through gate drain capacitance must return through the gate network and driver. If the resulting gate to source voltage becomes large enough, unwanted conduction may occur even though the logic command remains off.

Identify the coupling event

Capture the off device’s gate to source voltage together with the drain transition and relevant current. The Infineon explanation of induced MOSFET turn on describes the gate current caused by a rapid drain voltage change through gate drain capacitance. Treat the observed gate spike as a hypothesis to investigate, not automatic proof of channel current.

Verify probe common mode rejection and attachment. The same fast drain transition that excites the circuit can also create measurement error. Use an appropriate local source reference and minimize unintended probe loop coupling.

Trace the turn off impedance

Follow the path from gate through resistors, driver sink output, return connection, and device source. Include shared source inductance and the driver’s actual output state. A low schematic resistor value does not establish a low impedance path at every relevant frequency.

Review whether an active Miller clamp, separate turn off path, or negative gate bias is supported by the selected devices. Each option has its own voltage, timing, and layout requirements. Do not add negative bias without checking the gate’s permitted range and startup behavior.

Compare controlled changes

Change one relevant parameter at a time, such as the supported turn off resistance or switching transition rate, and observe both the gate waveform and power stage current. Record the effect on switching loss and voltage overshoot as well as on the unwanted spike.

Slowing the opposing device may reduce the excitation but alter efficiency and stress elsewhere. A clamp may improve local gate control only if its connection is effective during the critical interval. Verify the whole commutation after each change.

Establish an operating margin

Repeat at relevant bus voltage, temperature, load, and driver supply conditions. Include the state in which the driver supply is absent if the power circuit can still experience drain transitions. Check the device data for threshold variation and avoid treating a typical threshold as a guaranteed switching boundary.

Save synchronized voltage and current captures with the exact gate network. A defensible conclusion links the coupling mechanism, the implemented mitigation, and measured behavior over the required conditions. Merely reducing the visible spike in one capture does not establish that unintended conduction has been eliminated throughout operation.