Budgeting DESAT Blanking and Fault Turn Off Time

A desaturation protection circuit intentionally ignores part of the turn on transition so that normal switching does not look like a fault. That blanking also consumes time before a real fault can be acted on. Review the complete fault to current interruption interval, not only the comparator’s response specification.

Draw the protection timeline

Mark the turn on command, leading edge blanking, external capacitor charging, detection threshold, filtering, fault propagation, and gate discharge. The TI UCC21750 data sheet documents DESAT protection behavior, external blanking components, and soft turn off. These stages contribute different parts of the total response. Record their minimum and maximum values separately.

Determine how a fault already present at turn on differs from one that develops during conduction. The relevant starting state of the sensing node and timing logic may not be identical.

Calculate the adjustable interval

For a simplified constant current charging model, capacitor charging time is capacitance multiplied by voltage change divided by current. A hypothetical 100 pF capacitor charged by 0.5 mA through a 5 V interval takes 1 microsecond. Actual timing must include device thresholds, initial conditions, internal delays, leakage, and component tolerances.

Compare the resulting worst case response with the power switch’s documented fault withstand conditions. Do not compare a typical protection time with an unrelated short circuit rating measured at a different voltage, gate drive, or temperature.

Review false trip and shutdown stress

Inspect normal switching at relevant operating corners to establish the needed blanking and filtering. Excess capacitance may prevent nuisance trips while delaying fault response. Reducing it without examining switching noise can create repeated unwanted shutdowns.

Check the turn off path during a fault. Rapidly interrupting high current can cause voltage overshoot, while a slower controlled discharge extends energy dissipation. The protection design must account for both effects and the selected device’s limits.

Verify with an appropriate test sequence

Begin by checking the sensing and logic behavior using the driver’s supported test method before applying a high energy fault. Any power stage fault test requires a bounded setup appropriate to its voltage and stored energy. Capture current, device voltage, gate voltage, DESAT node, and fault output with suitable instrumentation.

Save component values, timing calculations, test conditions, and measured intervals. Include reset and retry behavior so the system cannot repeatedly reapply an uncontrolled fault. A valid protection record shows timely detection and acceptable shutdown stress, rather than merely demonstrating that the fault flag eventually changes state.