Checking Half Bridge Dead Time at the Power Devices

The dead time programmed in a controller is not necessarily the interval during which both power devices are off. Driver delays, gate networks, device behavior, and operating conditions alter the relationship between logic commands and current conduction. Verify the interval at the power stage before treating a firmware value as the result.

Define the two transitions

Analyze high side turn off followed by low side turn on, then analyze the reverse sequence. Include propagation delay variation and asymmetric gate charging or discharging. The two directions can have different timing margins even when the controller inserts the same delay.

The TI application brief on half bridge operation explains the role of dead time in preventing simultaneous conduction and the body diode conduction that can occur during the interval for the MOSFET arrangement discussed. The relevant reverse conduction mechanism depends on the actual device technology.

Measure more than logic signals

Capture both gate to source voltages, switch node behavior, and an appropriate current measurement. Use probes suited to the voltage references and transition rates. A gate voltage measured relative to board ground is not the high side device’s gate to source voltage.

Check probe delay and common mode response before comparing closely spaced edges. An apparent overlap can come from unequal measurement paths, while a real current spike can remain hidden by insufficient bandwidth or an unsuitable current path measurement.

Review the loss tradeoff

Excessive dead time can increase reverse conduction loss and affect subsequent commutation. Insufficient dead time can permit overlap. Do not minimize the programmed value solely to improve an efficiency reading without checking the waveforms and operating tolerances.

For a rough illustrative scale, 5 A flowing through a 1 V conduction drop for 100 ns transfers 0.5 microjoules in that interval. Actual loss depends on waveform, current direction, switching frequency, and device behavior. Use measured or supported models for the complete operating cycle.

Verify across relevant states

Repeat at the input voltage, load, temperature, and current directions that matter to the product. Include startup, braking or regeneration where applicable, and changes in operating mode. A delay established at one steady load may not cover every transition.

Save controller timing, driver and gate components, probe setup, and both commutation waveforms. The release decision should identify adequate overlap margin and acceptable loss for the tested operating envelope. It should not claim that a single nominal dead time is universally correct for every board using the same controller.