Embedded capacitance depends on a particular pair of conductive layers separated by a defined dielectric. A stackup that merely names a thin material can leave the functional layer relationship unclear. Verify material identity, thickness definition and plane assignment together before manufacturing release.
Define the complete layer pair
Mark both copper layers and the intervening dielectric in the stackup. Identify the relevant power and reference nets, including split regions and clearances. Keep material part designation and thickness tolerance tied to that exact position.
Qnity’s thin-laminate discussion describes paired power and ground layers using thin laminates for power-distribution applications. Its examples show why the dielectric and connected plane structure belong in the same design review; they do not eliminate application-specific PDN verification.
Clarify which thickness is being specified
| Dimension | Question |
|---|---|
| Dielectric | Does the value exclude the copper layers? |
| Copper | Which supplied and finished construction is intended? |
| Combined laminate | How does it contribute to total board thickness? |
| Inspection result | Which boundary and measurement method produced the value? |
Confirm the supplied construction with the material and PCB manufacturers. A purchasing description based only on overall laminate thickness may not establish the dielectric spacing assumed by the electrical model.
Compare the manufactured plane relationship
Review artwork and stackup revisions together. Identify any routing, clearance or plane-splitting change that affects the intended paired region. Keep layer-number conventions unambiguous when the fabricator describes a subcomposite separately from the final board.
For example, moving a power plane to simplify routing can leave the thin dielectric next to a different net. The named material remains in the BOM, but its intended electrical role has changed.
Where samples are used to verify thickness or electrical behavior, connect them to the same construction and process history. A generic material coupon may answer a material question without representing the final plane layout.
Keep section images labeled with the specific plane pair and physical board location. Measuring a neighboring thin dielectric can produce a plausible value while leaving the intended embedded-capacitance layer unverified. The sampling drawing should remove that ambiguity before preparation starts.
Release substitutions through both reviews
A proposed alternate should be reviewed for manufacturing compatibility and the resulting electrical model. Similar dielectric constant or nominal thickness alone does not establish complete equivalence.
Verify the relevant finished-board behavior with the product’s test plan. Embedded capacitance is one element of the power-distribution design, and its presence does not automatically justify removing every discrete capacitor.
The thin-dielectric handling guide addresses process exposure, while subcomposite records keep the buried material’s manufacturing history accessible.
Move from reading to a build-ready project
Use the fabrication and assembly checklists to prepare drawings, production files and test requirements.
Open the DFM checklist