Budgeting ADC Sampling Jitter at the Analog Input Frequency

Sampling-clock jitter creates a voltage error when the analog signal changes during the uncertain sampling interval. The resulting limit depends on the analog input frequency, not simply the ADC sample rate. Review this contribution before selecting a clock from a headline jitter value.

Define the timing terms

Analog Devices tutorial MT-007 distinguishes aperture delay from aperture jitter and derives the jitter-limited SNR relationship for a sinusoidal input. The result assumes jitter is the limiting error source, so it does not predict complete converter performance.

Record the ADC’s aperture-jitter information and the clock source’s relevant timing uncertainty. Include the distribution path and any additional components that affect the sampling edge. Keep deterministic delay separate from random sample-to-sample timing variation.

Calculate an initial limit

For the simplified sinewave case, jitter-limited SNR in decibels is minus 20 times the base-ten logarithm of two pi times input frequency times RMS timing jitter. An illustrative 10 MHz input with 1 ps RMS jitter gives approximately 84 dB.

That calculation does not establish an 84 dB system result. Other noise and distortion contributions remain. Use the equation to determine whether timing uncertainty is plausibly important and how much budget remains for the rest of the signal chain.

Combine compatible quantities

Use root-sum-square combination only when the contributions are appropriately modeled as independent random quantities. Check the integration bandwidth and measurement definitions behind clock-jitter values. Do not combine a peak-to-peak number with an RMS number or compare unrelated integration bands without conversion and justification.

Consider the input signal actually used by the product. A higher-frequency input can demand a cleaner clock even when sample rate remains unchanged. Conversely, a slow precision signal may be limited by a different mechanism long before the clock’s jitter contribution becomes dominant.

Verify the predicted sensitivity

Measure dynamic performance with a sufficiently clean analog source and a documented clock arrangement. Compare multiple input frequencies while holding relevant conditions constant. If practical, compare approved clock configurations to see whether the observed change agrees with the budget.

Retain input frequency, amplitude, sample rate, clock source and analysis bandwidth with each result. Account for the source and measurement system before attributing every performance change to the ADC. The resulting budget should identify which timing specification matters to the application and prevent selecting an unnecessarily expensive clock or overlooking an inadequate one because the sample-rate number appeared modest. Record whether the clock contribution includes the complete distribution path to the sampling pin.