Mapping Audio TDM Slots Across Multiple Converters

A time division multiplexed audio interface needs more than a shared bit clock. Every transmitter and receiver must agree on frame timing, slot positions, and the periods when each device may drive the data line. A mismatch can cause channel swaps, shifted words, or electrical contention.

Create a frame map

Draw one complete frame as numbered bit clock positions. Mark the frame sync transition, its active polarity and width, each slot boundary, and the meaningful sample bits inside each slot. Assign an owner to every transmitted slot.

The TI TLV320ADC6140 data sheet documents configurable serial word lengths and transmission offsets. Such controls are useful only when the receiving peripheral is configured to interpret the same timing. Do not assume that a setting called TDM implies a unique universal frame format.

Budget the bit clock

Calculate frame rate multiplied by slot count and slot width, including any implementation specific gaps. Eight 32 bit slots at a hypothetical 48 kHz frame rate require 12.288 MHz of bit clock if the frame contains exactly those 256 clock periods.

Compare the required clock with the limits and timing requirements of every connected device. Check setup and hold at the receiving pins using the actual clock direction and board delays. Converter sample resolution alone does not determine the serial slot width.

Check data line ownership

If several devices share one physical data line, verify their documented high impedance behavior outside assigned slots. Include startup, reset, disabled channel, and power down states. An unused slot is not automatically an undriven slot.

Use separate data lines or another supported arrangement if the devices cannot safely share the bus. Do not rely on matching transmitted values to prevent contention. Two outputs driving the same level temporarily does not establish a valid ownership scheme.

Verify with distinct channel signatures

Feed a recognizable signal or test pattern into one channel at a time. Confirm both its slot position on the wire and its destination in the receiver buffer. Check numeric alignment and sign extension separately from channel order.

Repeat after resets and configuration changes, especially when devices begin transmitting at different times. Save register settings, an annotated frame capture, and the channel to buffer map. The resulting record should let another engineer identify who drives each bit period and how that bit becomes a sample. That evidence is more useful than a statement that all channels produced some audio during a bench test.