Using Bridge Excitation Reversal to Separate Signal and DC Offset

A bridge measurement can contain a small DC offset from thermal junctions or the signal chain that does not reverse with the bridge excitation. Alternating excitation polarity can help separate that offset from the wanted response, but only when switching and conversion timing are coordinated.

Identify which terms reverse

The Analog Devices AD7195 data sheet describes AC bridge excitation with synchronized input and reference reversal. It also includes settling time between excitation switching and processing the analog signal.

Write a simple model for the two polarities. If one measurement is signal plus offset and the reversed measurement is minus signal plus the same offset, half their difference recovers the signal while half their sum estimates the unchanged offset.

Check the assumptions behind cancellation

The offset must remain sufficiently constant between the paired measurements. A rapidly changing thermal gradient or switching transient does not satisfy that assumption. The physical bridge input must also remain stable enough for the two readings to represent the same quantity.

For a hypothetical 1 mV bridge signal with a 20 microvolt constant offset, raw readings of 1.020 mV and minus 0.980 mV produce a 1.000 mV half difference. This ideal arithmetic does not account for switching errors, gain mismatch, or motion between readings.

Coordinate excitation and reference paths

Use the converter’s supported excitation mode or a fully analyzed equivalent architecture. Confirm allowed input and reference voltages in both polarities and during transitions. Do not reverse a reference on a converter that has not been designed to accept that condition.

Inspect switch control overlap, bridge drive impedance, and the effect of cable capacitance. Check that both polarities produce the intended excitation magnitude at the bridge rather than merely at the driver output.

Measure settled conversion windows

Observe bridge voltage, input nodes, and conversion timing together. Verify that the accepted samples exclude the transient after reversal. Increasing cable length or adding an input filter can lengthen settling beyond the original timing allowance.

Compare DC and alternating excitation results under a controlled thermal disturbance while keeping the mechanical load fixed. Also check response to a changing load, because cancellation that improves static offset can reduce the useful update rate or introduce dynamic error.

Save polarity mapping, reference behavior, settling captures, paired sample processing, and static and dynamic comparisons. A successful implementation cancels the intended polarity independent terms without creating a larger switching or timing error. Enabling an AC excitation bit alone does not establish that the complete bridge, cable, reference, and converter settle coherently before each accepted measurement.