Verifying SSI Encoder Clock Pauses and Frame Boundaries

An SSI encoder can return plausible position bits while a controller uses an incorrect frame boundary or pause interval. The clock burst and the quiet interval between bursts both matter. Review the exact encoder’s timing rather than assuming that any serial peripheral with the correct bit rate will acquire fresh position data.

Use the encoder’s timing definition

The Baumer PMG10 SSI operating manual specifies clock and monoflop timing and describes a device that sends zeroes after its word when clocking continues. Extra-clock behavior therefore should not be assumed identical across all SSI products.

Record word length, bit order, coding format, status fields, clock polarity, sampling edge, and required pause. Include any configurable position or speed fields that alter the frame length.

Capture the complete burst

Observe clock and data at the receiving electronics with enough history to include the preceding pause. Count actual clock edges and identify the first and last valid data bits.

Check whether a generic SPI peripheral adds unwanted clocks or inserts gaps inside a word. DMA or software scheduling can change burst structure even when the configured clock frequency is correct.

Verify fresh-data behavior

Move the encoder slowly through known positions and compare successive complete frames. Vary the interframe pause within the permitted operating conditions to confirm that the controller reliably starts a new acquisition.

For example, a too-short pause can create repeated or misframed information that looks like a temporarily stationary shaft. Correlate the electrical frame with an independent indication of motion instead of relying only on decoded position.

Include round-trip timing

The outgoing clock travels to the encoder and the returning data travels back. Review cable delay, encoder response, receiver delay, and the selected sampling edge together at the highest intended clock rate.

Measure with the actual cable and interface transceivers. A short laboratory connection can work while the installed cable shifts the returning data toward the receiver’s sampling boundary.

Test startup and interrupted transfers. Confirm how the controller recovers after an incomplete burst and whether a full pause is needed before the next valid word.

Keep Gray-code or binary conversion and status interpretation separate from electrical timing verification. A consistent software conversion error can obscure whether the underlying word was framed correctly.

Save the timing diagram, raw burst captures, pause measurements, and known-position comparisons. The completed review should establish both correct bit capture and fresh frame acquisition across the supported cable and rate range. A stable number on a display is insufficient evidence that the controller is reading the intended SSI word.