Checking SPICE Subcircuit Pin Order Before Trusting a Simulation

A simulation symbol can look correct while connecting its model terminals in the wrong order. The resulting circuit may fail obviously, or it may produce plausible but meaningless results. Check the model interface before using a simulation to approve component values or explain a board failure.

Read the model declaration

Analog Devices’ LTspice model-import guidance distinguishes a subcircuit from a primitive model and explains checking symbol pin order against the subcircuit declaration. A familiar symbol shape does not establish that mapping. The sequence in the model interface is what the simulator uses.

Record the model source, file revision, subcircuit name, terminal order, and any documented limitations. Build a small table mapping each model terminal to its electrical function and the corresponding symbol connection. Keep physical package pin numbers in a separate column where needed; they are not automatically the subcircuit order.

Inspect the generated connection

1. Confirm that the symbol invokes the intended model type and name.
2. Compare its connection order with the model declaration.
3. Inspect the generated netlist for the actual instance.
4. Check supply, reference, enable, and otherwise optional terminals.
5. Confirm that the intended model file is the one loaded by the simulator.

For example, two amplifier models may list their supply terminals in different positions. Reusing a symbol without checking that order can connect a signal node to a supply terminal inside the model. A successful file import does not detect the engineering mistake.

Run a simple functional sanity check

Use a small test circuit with an expected qualitative response. Check bias levels, polarity, enable behavior, and a modest input change within the documented operating range. Compare relevant results with the device data sheet or the model provider’s example.

Keep this validation separate from the complete board simulation. A large circuit can hide a mapping problem behind convergence messages or complicated interactions. The small test also provides a reusable reference when the model is updated.

Archive the symbol, model, netlist, and sanity-test result together. Avoid relying on a local search path that can silently load a different model on another workstation. If sharing restrictions apply to the model, preserve the source and acquisition instructions without redistributing it improperly.

Release simulation conclusions only after the interface is verified and the model’s scope is understood. Correct pin mapping is necessary, but it does not prove that the model represents every temperature, failure mode, or parasitic effect relevant to the physical board.