A precision reference with excellent DC specifications does not guarantee equally precise ADC results. The reference pin can present dynamic demands during conversion, and the PCB connection is part of the circuit that supplies them. Review the reference path separately from the analog input and digital interface.

Identify the conversion-time demand

TI’s SAR-ADC guidance describes transient current at the reference terminal during conversion. Its reference-buffer design compares a short, wide connection with a longer, narrower route, demonstrating that layout belongs in the reference design review. Follow the selected ADC’s requirements for buffering and local capacitance. TI: SAR ADC reference path; TI: reference-buffer optimization design.

List the ADC, reference source, any buffer, local capacitor, and isolation or damping components. Mark the operating sample rate and conversion sequence. A reference shared by several converters deserves review under their actual timing relationship, not just their average current consumption.

Trace both sides of the local loop

  • Follow the reference connection from the local capacitor to the ADC pin.
  • Trace the capacitor return to the ADC’s specified reference return or ground.
  • Review vias, narrow copper sections, and shared return paths.
  • Keep switching nodes and other noisy routes away from the reference network.
  • Check effective capacitor value and the buffer’s stability with the actual load.

For example, a capacitor placed beside the reference source may be electrically distant from the ADC after a long route across the board. Adding another capacitor at the ADC might help, but only if the resulting network is compatible with the buffer and device guidance. Placement should follow the dynamic requirement rather than visual symmetry.

Measure the behavior that affects conversion

Review ADC output data under representative input levels, sample rates, and channel sequences. If probing the reference node, use a method that does not materially change its load or inject noise. Record the probe, bandwidth, and operating mode. A steady multimeter reading cannot reveal every conversion-related disturbance.

Separate likely causes with controlled changes

If performance is poor, compare the reference path, input driver settling, supplies, clock, and digital coupling as distinct hypotheses. Change one relevant factor at a time and preserve the data. Do not attribute every code spread to the reference because it is easy to reach with a probe. Keep the approved reference components, routing, conversion settings, and validation results together so a later shared-reference expansion or capacitor substitution receives a meaningful review.

For multiple converters, repeat the evaluation with the worst relevant combination of simultaneous conversions and inactive channels.

Move from reading to a build-ready project

Use the fabrication and assembly checklists to prepare drawings, production files and test requirements.

Open the DFM checklist