Balancing Ripple and Settling in a PWM Analog Output

A filtered PWM output can provide an adjustable analog level, but the result depends on more than duty cycle. Timer resolution, high and low output voltages, filter loading and settling all contribute. Review these terms against the actual analog requirement before replacing a DAC with a PWM pin.

Define the useful output

TI’s PWM DAC application report examines the relationship between PWM frequency, duty-cycle resolution, filtering and settling. Its experimental examples demonstrate the tradeoff, while the appropriate values remain specific to the timer and analog load.

Specify output range, DC error, permitted ripple and the time allowed after an update. Identify the load resistance and capacitance, including any following amplifier or ADC. State whether the analog level must remain valid while firmware sleeps or reconfigures the timer.

Calculate the ideal and actual levels

For ideal high and low levels, the average output follows their duty-weighted values. An ideal 3.3 V waveform at 25% duty cycle averages 0.825 V. Real output resistance, supply variation and loading change that result and must be included in the error budget.

Determine the available duty-cycle steps at the chosen PWM frequency. Increasing frequency may make ripple filtering easier while reducing the number of timer counts per period. Check endpoint behavior, since some timer modes do not produce every nominal duty cycle exactly as expected.

Evaluate the filter at both time scales

Calculate residual carrier ripple and the response after a duty-cycle step. Use the complete loaded filter rather than an isolated RC equation when another circuit draws current from its output. Include component tolerances and capacitor characteristics relevant to the operating voltage.

For precision settling, define an error band around the final value. A 10% to 90% rise time is not the same as settling to a much tighter voltage tolerance. Choose the update schedule using the criterion that the downstream function actually requires.

Measure realistic updates

Observe large and small duty-cycle changes, steady-state ripple and output error across the intended range. Test with the final load and supply conditions. Include startup, timer disable and any mode change that can briefly alter the output pin state.

Keep the timer clock, register settings, filter values and measured performance together. If supply voltage is part of the analog scale, document how its variation is controlled or accounted for. Recheck the result when changing PWM frequency or low-power behavior. A justified PWM output specification should state the achievable voltage accuracy and response, rather than assuming that the timer’s bit count alone defines an equivalent DAC resolution.