Building a Power Sequence Map for a Multi-Rail Board

A multi-rail board needs more than a list of nominal voltages. Devices can impose requirements on the order, timing, ramp behavior, or relative levels of their supplies. Build a sequence map from those requirements before selecting enable connections or assuming that regulator startup delays will produce the right order.

Collect requirements by device

Analog Devices’ power supply sequencing application note discusses sequencing approaches and emphasizes checking the requirements of the actual powered devices. Its examples are device-specific. A sequence used for one FPGA or processor should not be treated as a general rule for all multi-rail components.

List each supply and the devices it powers. Extract required relationships for power-up and power-down separately. Include allowable ramp conditions, reset behavior, external signals, and any restrictions when one rail is present without another. Distinguish mandatory conditions from recommendations and unresolved questions.

Turn prose into observable events

1. Define the voltage or status event that represents each rail becoming valid.
2. Mark required ordering or timing relationships between those events.
3. Identify which circuit element enforces each relationship.
4. Review worst-case delay and threshold variation.
5. Define behavior when a required rail never becomes valid.

For example, connecting one regulator’s power-good output to another’s enable can create an ordering mechanism, but only if the power-good threshold, pull-up supply, and enable behavior meet the requirements. The connection’s name alone is not evidence that it works during every power state.

Include shutdown and interrupted starts

Rails can decay at different rates because of their loads and capacitance. An orderly startup does not guarantee an acceptable shutdown. Review discharge paths and any continuing supply from connectors or backup domains without assuming that all rails disappear together.

Test interrupted startup, short power removal, and restart while capacitors retain charge. Capture relevant rails and control signals in the same time reference. A sequence observed on separate oscilloscope screenshots can hide the relative timing that matters.

Preserve the requirement map, enforcing circuit, and representative captures together. State which limits were analyzed and which conditions were measured. If a load, regulator, capacitor, or external interface changes, check whether it affects the sequence or decay behavior.

The release should explain how the board reaches and leaves a valid operating state, including failure to start. That makes later debugging more precise: engineers can identify a violated relationship rather than debating whether a collection of individually correct rail voltages proves that the system is powered correctly.

Label every measured rail on the capture and retain the trigger condition used to establish the common time reference.