Test Channel Settling in a Multiplexed ADC System

A multiplexed acquisition board may measure each input accurately when sampled alone yet show errors during a scan. Switching from one channel to another creates a transient through the multiplexer, filters, amplifier and ADC input. The time available for that entire path to settle matters more than the multiplexer switching specification by itself.

Draw the timing that software actually uses

Mark channel selection, switch transition, acquisition interval, conversion start and data association. Identify which portion of the ADC cycle permits its input to settle. Use the selected converter’s timing model; a SAR input and a delta-sigma converter with digital filtering require different treatment.

Analog Devices’ multiplexed acquisition discussion explains the need for the complete signal chain to settle after a channel change. Switch timing, amplifier response and ADC input behavior all contribute. A quoted multiplexer bandwidth is not a direct guarantee of final conversion accuracy.

Create an informative scan pattern

Drive adjacent scan channels to deliberately different stable voltages within the allowed range. Alternate a low and high input, then compare the result with repeated sampling of each channel alone. Reverse the scan order and see whether the error follows the preceding channel.

Include representative source impedance. A low impedance laboratory source may hide settling problems that appear with a sensor, resistor divider or long cable. If channels have different filters, exercise the combinations that create the largest change at the shared path.

Measure the first valid result

Record the first several conversions after each switch. Vary the interval between selection and sampling while keeping other settings fixed. The resulting pattern helps distinguish residual settling from a stable gain or offset error. Preserve raw data rather than averaging away the transient immediately.

Discarding a conversion may be a valid design choice, but only if the remaining delay is sufficient under all required conditions. It also changes per-channel throughput and latency. Document which samples are discarded and how the retained sample is matched to its channel.

Choose fixes that address the bottleneck

Possible changes include timing, source buffering, filter values, amplifier choice or a different acquisition architecture. Each has consequences for noise, power, bandwidth or complexity. Slowing the scan is an informative experiment even when the final product cannot accept that speed.

Validate the final arrangement across the specified signal range, source impedance and operating conditions. Save the scan sequence with the hardware test results because a later firmware reordering can change the voltage steps and available settling time. Approval should cover the intended sequence, not merely a set of accurate single-channel readings.