Checking Bias and Data Patterns in an AC-Coupled LVDS Link

AC coupling can separate the transmitter and receiver’s DC operating points, but the receiver still needs a valid bias and the signal must survive the coupling network. Review both the input circuit and the transmitted pattern before approving capacitors in an LVDS path.

Establish the receiver’s DC state

Analog Devices’ AC-coupling discussion describes receiver bias and the importance of balanced signal content. Its examples also show that internal input structures can change the external bias arrangement required by a particular receiver.

Read the exact receiver’s input schematic and application guidance. Identify internal termination, bias and fail-safe functions rather than assuming they are present. Draw the DC state of both input pins with the transmitter disconnected through the coupling capacitors.

Review the transmitted pattern

List the clock duty-cycle range or the data coding and longest permitted interval without a transition. Include idle, training, startup and fault patterns. A repetitive balanced laboratory pattern can be easier for the link than the product’s real traffic.

For an illustrative continuously running clock, nominally equal high and low times differ from a clock that stops indefinitely in one state. Decide what the receiver must report while the clock is stopped and during its first returning edges. Do not evaluate only steady operation after the coupling network has settled.

Analyze the coupling time constant

Use the complete differential and bias network when assessing the effect of the capacitors. Include tolerances and the source and load impedances. Check the minimum signal amplitude and common-mode range at the receiver during the most demanding permitted pattern.

Increasing capacitance can change startup charging and recovery behavior as well as low-frequency response. Select the value from the receiver and transmitter guidance and the required pattern envelope, not from a capacitor value copied from an unrelated interface.

Verify acquisition and recovery

Measure receiver-pin voltages and the recovered output during startup, long idle intervals and return to traffic. Test duty-cycle and pattern extremes using the intended termination and bias components. Keep the measurement bandwidth and probe loading appropriate to the link.

Record the approved coding or clock behavior with the circuit. State which input states are valid, which invoke fail-safe behavior and which are outside the supported use. This makes a later firmware change to idle patterns or clock gating visible as an electrical-interface change, rather than assuming that an AC-coupled pair passes every digital waveform that fits within its nominal frequency rating.