Finding a Valid Sampling Edge for an Isolated Modulator Bitstream

An isolated delta sigma modulator can produce a valid bitstream that the receiving MCU samples at the wrong instant. The resulting conversion errors can resemble analog noise or a filter configuration problem. Establish the digital setup and hold window before changing the analog input network.

Identify the clock architecture

The TI report on clock edge compensation for isolated modulators distinguishes externally clocked and internally clocked interfaces and evaluates their timing at MCU filter inputs. The relevant clock path depends on which device generates it.

Draw clock source, modulator clock input, data output, and the receiving sampling point. Include buffers, level translators, and the MCU input qualification mode because they can alter the available timing.

Use minimum and maximum delays

Mark the earliest data change and the latest data validity relative to the actual sampling clock at the MCU. Compare both sides of the window with the MCU’s required setup and hold times.

Do not substitute a modulator’s data hold specification directly for the MCU’s hold margin without tracing the clock reference. Two parameters with similar names may be measured at different pins or relative to different clock edges.

Evaluate supported edge compensation

If the initial window is inadequate, consider documented clock inversion, delay, or peripheral sampling options. Recalculate both setup and hold after a change. Moving the sampling edge away from one boundary can move it toward the other.

Reducing the modulator clock can help some timing conditions, but it also changes the conversion chain’s data rate and latency. Keep those system effects visible instead of treating frequency reduction as a cost-free correction.

Measure and compare decoded data

Capture clock and data at the receiving pins with suitable timing resolution and limited probe loading. Check the intended edge across relevant supply and temperature conditions. Include any different clock rates used during startup or normal operation.

Apply known analog input conditions and compare the filtered result before and after a justified timing correction. Keep filter order, oversampling ratio, and scaling unchanged during that comparison so the digital interface effect is isolated.

Save the path diagram, delay limits, peripheral mode, sampling edge, measured window, and conversion evidence. A successful interface establishes a valid acquisition interval rather than simply selecting the edge that gives a plausible number on one board. Recheck the budget when substituting a modulator or changing MCU input qualification because either can shift the bitstream timing without altering the analog schematic.