An I2C pullup should satisfy both a high-state rise-time requirement and a low-state drive requirement. Choosing a familiar value such as 4.7 kilohms without checking either condition can work on a short prototype and fail after a cable, protection device or additional module is added.
Establish the two bounds
The minimum resistance is constrained by the current that the weakest relevant device can sink while maintaining an acceptable low voltage. The maximum resistance is constrained by bus capacitance and the allowed rise time. Texas Instruments’ pullup calculation report derives these relationships, including the 0.8473 RC expression for a rise measured between 30 and 70 percent of the supply.
Use the actual operating mode, voltage and device guarantees. As an illustrative calculation, a chosen 300 nanosecond rise allowance with 100 picofarads gives an upper resistance of about 3.54 kilohms using that model. This result is only one bound; it does not approve that value or establish the appropriate timing limit for every bus.
Count what is physically connected
Include device pins, traces, connectors, cables, switches and protection capacitance. Check every population variant and plug-in module. Several modules may each contain pullups, producing a much stronger combined pullup than the schematic of the main board suggests.
For example, two equal 4.7 kilohm pullups to the same rail act as 2.35 kilohms. Confirm their rail connections as well as their resistance. Pullups to different voltage domains require an interface compatibility review rather than a simple parallel-resistance calculation.
Treat buffered segments separately
If a buffer or level translator divides the bus, follow its specific requirements for each side. Some devices introduce offsets, direction behavior or pullup constraints that a simple passive-bus model does not capture. Verify that every receiver still recognizes the resulting low and high levels.
Check unpowered devices and removable modules. An inactive peripheral can load a line or prevent it from rising, depending on its I/O behavior. A successful transfer with all supplies present does not establish behavior during power sequencing.
Measure the assembled result
Observe rise time and low-level voltage at representative endpoints under the intended loading. Include instrument capacitance when interpreting the waveform. Exercise different devices driving low, because the controller may have stronger outputs than one peripheral.
If the calculated bounds do not overlap, changing only the resistor cannot satisfy the assumptions. Revisit capacitance, speed, segmentation or device selection. Keep the calculation and measured waveforms with the approved topology so a later module or cable change triggers a meaningful electrical review.
Move from reading to a build-ready project
Use the fabrication and assembly checklists to prepare drawings, production files and test requirements.
Open the DFM checklist