Testing I2C Arbitration Loss with Multiple Controllers

Two controllers can legally share an I2C bus only when their hardware and software support the required coordination. A collision is not handled by simply waiting a fixed delay after a failed transfer. The losing controller must recognize arbitration loss, stop interfering, and preserve enough transaction state to retry safely.

Observe SDA while SCL is high

NXP’s I2C specification defines bitwise arbitration and clock synchronization. A controller that releases SDA to transmit a high level but observes a low level while SCL is high loses arbitration. The winning transaction continues. Read the MCU peripheral’s handling rules as well, including which status flags and interrupts distinguish arbitration loss from a target NACK.

For a reproducible experiment, arrange for two controllers to begin nearly together and send different address or data bits. Capture both controllers’ request markers with SDA and SCL. The bus waveform alone may show a valid winning message while hiding that the losing firmware incorrectly reports success.

Test the software consequences

A failed attempt may be safe to repeat for a register read but not automatically safe for a command with a side effect. Determine which bytes were accepted and whether the target operation is idempotent. Use an application-level transaction rule where bus-level arbitration alone cannot establish the final state.

• Confirm both controllers use open-drain signaling on the shared lines.
• Check that every buffer or isolator supports the intended multi-controller behavior.
• Verify the losing controller stops driving as required.
• Wait for a valid bus-free condition before retrying.
• Bound repeated retries and report persistent contention.

Include clock and recovery interactions

Controllers with different clock timing can synchronize on the wired bus. Test the supported speed and stretching behavior through the complete path. Do not run a stuck-bus recovery sequence merely because arbitration was lost; recovery clock pulses during a valid winning transfer would introduce a new error.

Exercise reset of either controller during contention and verify the remaining controller can continue under the documented system rules. Use clock-stretch compatibility checks and stuck-line diagnosis to keep those distinct conditions separate. Record the bus capture and both firmware outcomes. A successful test requires one complete winning transaction and an explicit, recoverable losing state, not simply the absence of a hung bus.