Checking a Glitchless Clock Switch When an Input Stops

A clock multiplexer described as glitchless may avoid short output pulses while still introducing a long gap or requiring edges from an input to complete switching. That can be acceptable for one receiver and disruptive for another. Review stopped clock behavior separately from switching between two healthy sources.

Read the switching sequence

The Si53301 manufacturer data sheet describes switching between valid input clocks and the associated output low interval. Its sequence depends on input clock edges, illustrating why the exact missing-input behavior must be understood.

Identify supported frequency ratios, selection timing, and output state during the transition. Glitchless does not necessarily mean phase continuous, gapless, or suitable for an arbitrary stopped input condition.

Define the failure cases

List switching while both clocks run, switching to an absent source, and switching away from a source that has stopped high or low. Treat these as different cases. Determine which are covered by the component’s documented operation.

Record what detects the missing source and what initiates selection. A mux that accepts a select signal does not necessarily include an independent loss-of-clock detector.

Measure the output transition

Capture both inputs, select, and output together. Inspect the shortest high and low pulses as well as the longest gap. A display triggered only on normal clock edges can miss a delayed handover or an output that remains stopped.

Vary the relative phase of two running sources and repeat enough transitions to exercise different alignments. For stopped-source tests, use a controlled clock stop method consistent with the source and mux specifications.

Verify receiver recovery

Determine whether the downstream receiver tolerates the measured gap and any phase discontinuity. A PLL, processor clock input, or serial interface can have its own requirements for missing edges and restart. Check status and functional behavior after the handover.

If a reset or reinitialization is required, connect it explicitly to the switching state machine. Do not infer uninterrupted operation from the absence of narrow pulses alone.

Save the documented switch sequence, tested input conditions, pulse width and gap measurements, and receiver response. A useful result states which source failures can be recovered and what interruption remains. This prevents a component’s glitchless label from becoming an unsupported system claim that every clock failure can be handled without a missing edge, phase change, or downstream recovery action. Include an explicit timeout in the system evaluation so a switch that never completes is distinguishable from a permitted long handover.