Keeping a GaN Gate Drive Inside the Device Voltage Window

A gate drive that is routine for a silicon MOSFET may be unsuitable for an enhancement mode GaN device. The usable turn on voltage and maximum gate limits depend on the selected technology and part. Review the entire gate waveform, including overshoot and undershoot, before connecting a familiar driver to a new transistor.

Start with the exact device limits

Record recommended turn on voltage, permitted negative voltage, absolute maximum ratings, and any pulse duration qualifications. The EPC guidance on selecting GaN drivers and controllers emphasizes appropriate gate drive voltage and compatible driver behavior for its eGaN devices.

Do not generalize one manufacturer’s voltage recommendation to all GaN products. Integrated power stages, enhancement mode transistors, and other implementations can have different external interface requirements.

Budget the delivered voltage

Include driver supply tolerance, regulation, startup overshoot, bootstrap behavior where applicable, and voltage drop in the drive path. Use component tolerances rather than only nominal values when combining those contributions. Check the maximum positive gate voltage and the minimum voltage needed for the intended conduction performance.

Evaluate the waveform relative to the transistor’s local source. Source inductance can make the effective gate voltage differ from the driver output measured against a distant return. A nominal supply measurement cannot reveal that difference.

Measure without adding a dominant loop

Use a probe and attachment suitable for the edge speed and small physical gate loop. Review probe loading and common mode performance. Long connections can create an apparent ringing waveform or alter the circuit enough to hide its original behavior.

Observe turn on, turn off, and the opposing switch transition in a half bridge. Include startup and driver undervoltage states if the power node can move while the driver is not fully powered. Capture the complete voltage envelope instead of only the settled high level.

Evaluate changes as a system

Adjust gate resistance, layout, or driver selection only within the supported design guidance. Recheck switching loss, voltage overshoot, and unwanted turn on after any change. Slower edges can reduce one disturbance while changing thermal performance and dead time behavior.

Save the device and driver revisions, supply range, local gate waveform, probe setup, and operating conditions. The evidence should show that the gate remains within its reviewed window across the intended envelope. A successful short bench run at nominal input is insufficient to establish that startup, temperature, and maximum switching stress have the same margin. Include those states explicitly in the validation record.