Scheduling Delta-Sigma Measurements Using Conversion Latency

The output data rate of a delta-sigma ADC does not necessarily equal the rate at which a scanning system obtains settled readings from different channels. Filter latency, startup delay and configuration changes can all affect the first usable result. Build the schedule from the documented conversion sequence.

Identify what restarts the sequence

TI’s conversion-latency application note describes how ADC modes, digital filters and programmable delay affect conversion timing. Its ADS124S08 examples distinguish initial conversion behavior from subsequent results and include delay intended to accommodate external settling.

Record the selected filter, data-rate setting, clock source and conversion mode. List the register writes or control events that restart conversion or reset the filter. A channel change can have timing consequences even when gain and reference settings remain unchanged.

Draw one complete scan

Start with the last valid result from the previous channel. Add the configuration transaction, any analog settling interval, the converter’s required latency and the time to read and store the next result. Include communication overhead that cannot occur concurrently with another operation.

For an illustrative four-channel scan, do not divide one channel’s continuous data rate by four without checking the first-result timing after every switch. A low-latency filter and a higher-order filter at the same nominal output rate can require different schedules.

Keep analog and digital settling distinct

The ADC’s internal filter timing does not prove that an external sensor, amplifier or RC network has settled. Determine that external response separately, especially after large channel-to-channel voltage steps or excitation changes. Use the converter’s programmable delay only within its documented purpose and limits.

Define the error allowed in the first retained reading. Decide whether a result must be discarded based on the actual device behavior and measured external response. Avoid a blanket instruction to discard an arbitrary number of samples without evidence that it covers every configuration.

Verify the firmware timeline

Capture configuration traffic, conversion-control signals and data-ready transitions together. Tag stored samples with their channel and relevant configuration. Compare timestamps against the planned scan and check the behavior when a read is delayed or a conversion is restarted.

Retain the measured first-result time and complete scan time for each supported filter configuration. Include clock tolerance and exceptional paths where they affect the deadline. When firmware changes a filter or power mode, review the timing budget again. The resulting schedule describes when a trustworthy channel reading exists, rather than merely how often a converter can emit words during uninterrupted operation.