Checking DAC Output State Through Reset and Brownout

A DAC output that starts at the intended value after a clean power cycle may behave differently during a shallow supply dip or controller-only reset. Review each event separately. The downstream circuit responds to the analog voltage throughout the transition, not just to the final register value read by firmware.

Identify the exact device option

The TI DAC80508 family data sheet describes device-dependent zero-scale or midscale power-up behavior, reset conditions, and clear-function variants. It also defines supply conditions needed to ensure a power-on reset occurs.

Record the complete orderable part number and the controls available on that variant. Do not infer clear-pin behavior from another member of the family that shares the same basic converter resolution.

Map each reset event

List full power removal, analog-supply dip, interface-supply dip, software reset, clear assertion, and controller reset. For each event, identify whether the DAC is expected to reset, retain data, or remain outside guaranteed operating conditions.

Include reference startup and any external output amplifier. A reset code does not by itself guarantee a particular system output while the reference or amplifier supply is still changing.

Capture the analog trajectory

Measure supply rails, reset or clear controls, reference, and representative DAC outputs on one timeline. Use the actual output load and sufficient record length to include startup settling.

Test from more than one previously programmed output value. A retained high code during a brief interruption can produce a different recovery trajectory from a retained low code, even when both eventually receive the same initialization command.

Exercise incomplete power cycling

Apply controlled supply interruptions within the device’s documented test and operating constraints. Vary duration and depth around the regions relevant to the product’s power behavior. Record whether a reset is guaranteed, absent, or unspecified under each condition.

For example, unplugging and immediately reconnecting a product may leave internal rails partially charged. A bench test that always waits for complete discharge does not cover that use case.

Check firmware ordering so reference configuration, range settings, data loading, and output enabling produce the intended result. Confirm the default state of control pins while the processor is booting, including any interval when its pins are configured as inputs.

Save the event matrix, measured output trajectories, and initialization sequence. The acceptance criterion should describe allowable analog behavior during each supported event. A correct power-on default is one part of that evidence; it does not establish the behavior of every brownout, partial reset, or retained-state recovery.