Separating Common-Mode Transient Artifacts from Real Shunt Current

A current-sense amplifier can see a small differential shunt voltage while both inputs move rapidly through a large common-mode transition. The output disturbance around that edge may not represent a real change in current. Review dynamic common-mode behavior before setting the sampling instant.

Use the relevant dynamic specification

The INA240 data sheet describes enhanced PWM rejection intended to reduce output artifacts from large common-mode transitions. This behavior is distinct from a static common-mode rejection number and must be evaluated under applicable operating conditions.

Record the differential signal range, common-mode voltage range and transition rate. Include undershoot and overshoot at the actual input pins. Check the selected device’s operating and absolute limits separately, including any input filtering or protection network.

Observe the edge in context

Capture the switching node, shunt-related signal and amplifier output on a common time axis using a suitable measurement arrangement. Identify the interval during which the common-mode voltage changes and the time required for the output to return to the needed accuracy.

Do not assume that every output spike is an amplifier artifact. Parasitic inductance, current redistribution and probing error can also create a measured differential pulse. Use independent evidence where practical to distinguish real current behavior from common-mode conversion in the sensing path.

Review filter symmetry

Check the resistors and capacitors connected to both inputs and how their tolerances affect the transient response. Follow the current-sense manufacturer’s guidance for filtering, because added input resistance can interact with the device and change gain or rejection.

Keep the shunt pickup paths and reference connection representative of the final board. A test performed with long temporary wires may introduce a different disturbance from the production layout. Record the physical measurement locations and any modifications.

Set a justified sampling window

Determine when the current-sense output is valid for the required error budget after each edge. Include the shortest PWM pulse and all permitted duty cycles. Ensure that the ADC’s acquisition interval fits inside the valid window, not merely that its trigger occurs after a chosen delay.

Retain the waveform, error criterion and timing margin with the sensing configuration. Repeat the review when changing switching speed, input filtering or amplifier type. This provides a concrete basis for blanking and sampling decisions and prevents a good DC accuracy specification from being mistaken for proof that every point on a rapidly switched current-sense waveform is equally suitable for measurement. Identify the exact ADC acquisition interval on the timing plot.