A CAN FD node can communicate at the arbitration rate but report errors when the faster data phase is enabled. The local delay from the controller’s transmit output through the transceiver and back to its receive input may become significant relative to the data bit time. Review transmitter delay compensation as one part of the timing analysis.

Separate local and network timing

Draw the controller transmit pin, transceiver, bus connection, transceiver receive output, and controller receive pin. Identify the local loop delay separately from cable propagation and other nodes’ timing. Compensation for the local transmit monitoring path does not remove every network timing constraint.

The STMicroelectronics AN5348 FDCAN application note describes a secondary sample point based on measured transmitter delay and a configured compensation offset. Use the procedure and units specified for the actual controller implementation.

Check the configured time units

Record kernel clock, prescalers, nominal timing, data timing, and compensation fields. Determine which clock defines each field. A number copied from another project can represent a different duration when the peripheral clock or prescaler changes.

As an illustrative scale, a 5 Mbit/s data phase has a 200 ns bit time. A local delay of tens of nanoseconds is therefore a meaningful fraction of that interval. This observation does not prescribe a compensation value; the value must follow the controller’s timing model and supported range.

Measure and test at the pins

Capture transmit and receive signals with a common timing reference and adequate instrument resolution. Check the transceiver mode, supply, and loading used during the measurement. Review documented delay variation with operating conditions instead of relying only on one room temperature capture.

Exercise representative CAN FD frames and data patterns while monitoring the relevant error indicators. Compare behavior at a conservative data rate and the intended rate. Preserve the configuration for each run so an improvement can be tied to a specific timing change.

Retain the rest of the interface review

Verify termination, topology, signal quality, oscillator accuracy, and the timing requirements of the connected nodes. A setting that suppresses one local error is not proof that the complete bus has sufficient margin.

Save the clock calculation, compensation configuration, measured local delay, and error results. The final decision should explain how the controller samples its own transmitted data and how the broader network remains valid. This avoids treating transmitter delay compensation as a universal cure for a CAN FD link that fails at higher speed.

Move from reading to a build-ready project

Use the fabrication and assembly checklists to prepare drawings, production files and test requirements.

Open the DFM checklist