Verifying ADC Line Frequency Rejection with the Actual Clock

A precision ADC’s digital filter can strongly reject line-frequency interference under specified conditions, but the rejection is not identical at every data rate and clock setting. Check the actual filter response and timing source before assuming that selecting a low output rate removes all 50 Hz or 60 Hz contamination.

Identify the supported filter mode

The TI ADS124S08 data sheet describes line-cycle rejection for particular data-rate and filter configurations. It also relates filter behavior to the ADC clock, making clock choice part of the rejection review.

Record the programmed filter, data rate, clock source, and clock tolerance. Confirm that the running register configuration matches the one used in the data-sheet response plot.

Inject controlled interference

Apply a stable wanted signal with a known interference component while keeping the ADC and input amplifier within their valid ranges. Measure the injected component at the appropriate input boundary rather than relying solely on the source setting.

Start at the nominal line frequency, then sweep around it over the range relevant to the application. A deep result at one exact frequency does not describe rejection across a varying interference frequency.

Include clock variation

Where the hardware permits a controlled clock adjustment, repeat the sweep at representative clock offsets. Otherwise, evaluate the specified clock tolerance against the documented filter response and confirm meaningful temperature conditions experimentally.

For example, changing from an external clock to an internal oscillator can alter the placement of a narrow rejection region. A firmware change that preserves the nominal output-rate label may still require a new rejection assessment.

Check the signal before digital filtering

Observe whether interference causes clipping or overload in the analog input path. A digital notch cannot restore information lost when an amplifier or converter exceeds its usable range.

Inspect harmonics and other interference frequencies separately. A favorable fundamental-frequency measurement does not establish rejection of every spectral component associated with the same power source.

Measure settling and update latency in the chosen filter mode so the application still receives useful readings at the required time. If channels are multiplexed, include the actual switching schedule and valid-data rules.

Save the configuration, clock assumptions, interference sweep, measured residual, and analog headroom checks. State rejection over a defined frequency interval and operating range instead of reporting only the deepest point. The resulting evidence connects the advertised filter capability to the actual board clock and signal conditions under which the product must make its measurement.