Recovering ADC Data Ready Timing After a Missed Read

An ADC interface can work perfectly in a tight polling loop and fail when the processor services another interrupt. Data-ready behavior depends on output mode, internal buffering, and whether conversion data have been read. A missed transaction can change the next edge sequence without changing the configured conversion rate.

Read the device-specific pause behavior

The ADS131M04 data sheet describes pulse and level DRDY formats and a two-sample internal buffer. It also provides recovery procedures after a pause. This is a useful example of why an interrupt pin must be interpreted with the converter’s buffering rules rather than treated as a generic periodic clock.

For a hypothetical 4-kSPS acquisition, new results occur every 250 microseconds. If a high-priority task blocks service for 800 microseconds, a two-entry buffer cannot preserve every sample. A later burst of successful SPI transfers does not prove continuity. The application needs a way to mark the gap and reestablish which result belongs to which interval.

Inject deliberate service delays

Capture DRDY, chip select, serial clock, and a processor service marker. Introduce delays shorter than one sample interval, slightly longer, and several intervals long. Compare the observed sequence with the specified behavior. Check interrupt polarity, edge versus level configuration, and any minimum pulse width recognized by the processor’s input circuit.

• Measure worst-case interrupt latency under realistic firmware load.
• Verify the full SPI transfer fits within the available read window.
• Exercise startup, standby exit, and resumed collection after a pause.
• Use the documented resynchronization or buffer-draining procedure.
• Flag discarded or uncertain samples explicitly in the data stream.

Separate sample validity from bus success

A CRC-valid frame proves a particular communication check passed; it does not prove that no conversion was missed. A correct channel value can also be assigned the wrong timestamp. If multiple channels use phase adjustment, verify the selected DRDY source and the availability of each channel’s result before assembling a simultaneous record.

Combine this work with SPI timing margins and buffer service budgeting. Keep the recovery state machine and a captured delayed-service example with the board’s interface notes. That makes a firmware scheduling change reviewable against actual acquisition continuity rather than only against average bus throughput.